1. Field of Invention
The present invention relates generally to circuit design, and more specifically to methods for designing circuits using equation-based optimization.
2. Description of Related Art
The need for more efficient and effective equation and software-based methods for integrated circuit design has become paramount for today's businesses involved in the development of electronic and computer devices. Over the last decade, various such methods have been introduced in the arenas of both digital and analog circuit design. As the level of sophistication of electronic devices and their constituent components has increased, so too have the requirements for design solutions uniquely tailored to this level of sophistication. The desire for more precise and efficient methods has become evident as the sophistication of modern integrated circuits continues to increase exponentially.
While many types of digital integrated circuits are designed using an automated synthesis flow based on a library of pre-designed cells, other types of circuits are still custom designed, especially those where high performance is needed (e.g., microprocessors, mixed-signal circuits, and the like). Custom circuit design is typically far more complex than standard-cell based design. In custom circuit design, the basic building blocks include transistors, capacitors, interconnects, and similar devices, rather than fixed size gates. The synthesis process in custom design is manual rather than based on a logic synthesis tool. Further, the physical custom designs are not structured and may take a variety of forms.
In custom circuit design, the designer has virtually complete control over the circuit topology, specific sizes, cell layout and overall circuit physical design. The fact that the designer has little design constraints (e.g., the designer can use any device size within limits rather than just a fixed size), allows him or her to be able to create very high performance circuits. However, this gain in performance comes at a cost: complexity of the design process.
Unfortunately, the complexity of the design process has only increased over time. The reasons include, among others, the increased technology scaling, the higher levels of on-chip integration, the fact that analog design cycles have become as short as digital design cycles, and the large process parameter variations in current process technologies. Most custom design is performed manually by a reduced number of expert designers using the same techniques that were used twenty years ago. The problem is exacerbated by a shortage of custom circuit designers, especially analog designers. As consumer demand for more sophisticated products shipped faster to market has grown, the need for more efficient design tools has become more critical to companies attempting to accommodate these schedules.
In the traditional custom design method, the designer typically starts from a set of specifications and a target process. Then, the designer chooses a promising circuit architecture or topology. After which, the designer proceeds to the component sizing process, i.e., to determine the sizes or values of the components that achieve the requirements of the desired performance. Compared to designs using a standard cell library, the number of design variables is generally relatively small (often only a few tens or hundreds). Unlike standard cell design, the performance of custom circuit designs are typically very sensitive to small changes in design variables. The designer must be very precise in determining all of the design variables, or the resulting circuit performance will be poor at best. More likely, the circuit simply will not function.
Additionally, each design variable using the custom design approach typically affects all the performance indices in a complex, highly nonlinear way. The traditional approach to component sizing repeatedly cycles through circuit simulation with a tool like SPICE, and updating, or tweaking, the design variables either manually or with an automated search engine.
This custom design flow nevertheless enjoys a significant advantage in that circuits may be hand-crafted to maximize performance. The designer typically spends a long time tweaking the circuit and trying to obtain the greatest amount of performance possible out of it in light of the constraints within which he or she must work. Unfortunately, this custom design flow has several disadvantages. First, the process is extremely time consuming. In fact, given the choice, designers would spend longer time tweaking the variables on their designs than schedules permit. Generally, it is very difficult to determine when to stop tweaking a circuit to achieve maximum performance. Also, the custom design approach relies heavily on an experienced custom designer not only to create a completely new custom circuit from scratch, but also to port an existing circuit to a new process technology. The custom design flow does not encapsulate the knowledge of the experienced designer and as such it cannot be used later by a less experienced designer, or even re-used by the experienced designer to modify the existent circuit efficiently.
In an attempt to overcome many of these obstacles, equation-based synthesis methods for custom circuit design have been implemented or proposed in the literature. In equation-based methods, the design problem is cast as a mathematical optimization problem, which is then solved by a numerical algorithm. The resulting problem is cast as either a general nonlinear optimizer problem or as a convex optimization problem such as a geometric program or a linear program. To solve the general nonlinear optimization problems resulting in analog design, classic numerical optimization methods, such as steepest descent, sequential quadratic programming, and Lagrange multiplier methods have been used. Also, various known general purpose optimization codes, and other Computer-Aided-Design (CAD) methods for analog and mixed-signal circuit design based on classical optimization methods, may be used. Still other equation-based methods for custom digital circuit design are used (either generally nonlinear or convex), including for the purpose of gate sizing and design of ground-power networks.
Geometric programming is a type of equation-based method for identifying circuit parameters in a custom circuit design. This method has been widely used, for example, in transistor and wire sizing for Elmore delay minimization in digital circuits. Generally, a geometric program involves minimizing posynomial functions subject to posynomial and monomial constraints to provide a set of specific optimized design parameters. Advantageously, a number of commercially available programs exist for efficiently solving complex optimization programs in geometric form. Such programs include, for example, MOSEK. There are also some publicly available solvers for solving geometric programs.
A geometric program can be reformulated as a convex optimization program by changing variables and by considering the logarithms of the functions involved. A convex optimization method is a type of equation-based method that solves a special type of optimization problem—namely, a convex optimization problem. In this method, the circuit requirements and performance are described by a set of analytical design equations that have a special form. Once in this form, the design problem can be transformed into a convex optimization problem. This type of mathematical optimization problem can be solved globally very efficiently, even when the problems are large scale and nonlinear. The fact that one can solve large scale, nonlinear convex optimization problems is advantageous in many instances because it can potentially take thousands of highly nonlinear equations to accurately predict the performance of a complex block, like a phase-locked loop (PLL) or data converter.
Even though the convex optimization method is just a special type of equation-based method, it does not necessarily suffer from the traditional accuracy problem of existing equation-based methods. In particular, even though the type of equations that can be used is restricted (i.e., the equations must be convex) they can still be highly nonlinear and complex and can be used to represent intricate circuit behavior.
One very great advantage of convex optimization, compared to general purpose optimization methods, is that the global solution is always found, regardless of the starting point. Also, infeasibility is unambiguously detected. That is, if the methods used do not produce a feasible circuit-based solution, they may produce a certificate that proves that the problem is infeasible. When the geometric program is solved, a complete sensitivity analysis of the problem may also be obtained without any additional computational effort. These sensitivity numbers may provide extremely useful design insight.
Another important practical advantage with convex optimization problems is that they may be solved very efficiently. In the last decade, powerful interior-point methods for solving general convex optimization problems have been developed. These methods can solve large problems, with tens of thousands of variables and hundreds of thousands of constraints, very efficiently (e.g., in a few minutes on a modern PC). Problems involving tens of variables and hundreds of constraints are considered small, and can typically be solved on a modern PC in less than one second.
In order for a designer to use convex optimization methods, the designer is necessarily restricted in the type of equations that can be used to describe the problem. However, in circumstances where the method can be applied, great algorithmic benefits are available. Even though the circuit designer is restricted to using a convex formulation, the method can be applied to a wide variety of circuit design problems.
Various shortcomings for existing equation-based methods, including geometric programming and convex optimization methods, are widely evident. For example, using geometric programming to produce a convex problem, the circuit device models must be approximated in posynomial format. Where, as presently, simple design parameters are used as variables in the posynomial functions identifying the performance specifications associated with the geometric or convex optimization program, such as in the method disclosed in U.S. Pat. No. 6,269,277 issued to Hershenson et al., extra errors are introduced. As an illustration, these errors may become significantly pronounced in deep submicron CMOS processes. The geometric programming method is typically not accurate for transistors having a small channel length, where channel length modulation, body-effect, drain-induced barrier lowering, vertical field mobility degradation, and other non-idealities complicate the equations for the transistor parameters As another example, transistors operating in the subthreshold or weak inversion regions of operation cannot be modeled accurately using geometric programming methods. Numerous other examples exist in circuit design where design parameters cannot be accurately optimized where the equation-based method is limited to geometric programming form using simple design parameters.
Yet another shortcoming of geometric programming based methods is that general linear constraint functions cannot be used. In particular, geometric programming is limited to posynomial inequality and monomial equality constraints. This characteristic of geometric programming results in several practical disadvantages in the realm of circuit design. For example, the first step in almost all analog circuit design problems is to determine an appropriate direct current (DC) operating point. Kirchoff's Voltage Law (KVL) and Kirchoff's Current Law (KCL) assist the engineer in algebraically solving for this DC operating point. These two basic laws which govern almost all analog circuits, however, typically result in posynomial equality constraints, and thus cannot be handled using geometric programming.
Accordingly, a need exists in the art for an efficient equation-based method to be used in any circuit design problem for accurately modeling a wide variety of design parameter types under a wide variety of circuit conditions.